vishay siliconix si2305cds document number: 64847 s10-0720-rev. c, 29-mar-10 www.vishay.com 1 p-channel 8 v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 definition ? trenchfet ? power mosfet ? 100 % r g tested ? compliant to rohs directive 2002/95/ec applications ? load switch for portable devices ? dc/dc converter product summary v ds (v) r ds(on) ( ) i d (a) d q g (typ.) - 8 0.035 at v gs = - 4.5 v - 5.8 12 nc 0.048 at v gs = - 2.5 v - 5.0 0.065 at v gs = - 1.8 v - 4.3 ordering information: SI2305CDS-T1-GE3 (lead (pb)-free and halogen-free) g to-236 (sot-23) s d top view 2 3 1 * marking code si2305cds (n5)* s g d p-channel mosfet notes: a. surface mounted on 1" x 1" fr4 board. b. t = 5 s. c. maximum under steady stat e conditions is 175 c/w. d. t c = 25 c. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds - 8 v gate-source voltage v gs 8 continuous drain current (t j = 150 c) t c = 25 c i d - 5.8 a t c = 70 c - 4.7 t a = 25 c - 4.4 a, b t a = 70 c - 3.5 a, b pulsed drain current (10 s pulse width) i dm - 20 continuous source-drain diode current t c = 25 c i s - 1.4 t a = 25 c - 0.8 a, b maximum power dissipation t c = 25 c p d 1.7 w t c = 70 c 1.1 t a = 25 c 0.96 a, b t a = 70 c 0.62 a, b operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a, c t 5 s r thja 100 130 c/w maximum junction-to-foot (drain) steady state r thjf 60 75
www.vishay.com 2 document number: 64847 s10-0720-rev. c, 29-mar-10 vishay siliconix si2305cds notes: a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = - 250 a - 8 v v ds temperature coefficient v ds /t j i d = - 250 a - 9 mv/c v gs(th) temperature coefficient v gs(th) /t j 2.5 gate-source threshold voltage v gs(th) v ds = v gs , i d = - 250 a - 0.4 - 1 v gate-source leakage i gss v ds = 0 v, v gs = 8 v 100 na zero gate voltage drain current i dss v ds = - 8 v, v gs = 0 v - 1 a v ds = - 8 v, v gs = 0 v, t j = 55 c - 10 on-state drain current a i d(on) v ds - 5 v, v gs = - 4.5 v - 10 a drain-source on-state resistance a r ds(on) v gs = - 4.5 v, i d = - 4.4 a 0.028 0.035 v gs = - 2.5 v, i d = - 3.8 a 0.039 0.048 v gs = - 1.8 v, i d = - 2 a 0.053 0.065 forward transconductance a g fs v ds = - 4 v, i d = - 4.4 a 17 s dynamic b input capacitance c iss v ds = - 4 v, v gs = 0 v, f = 1 mhz 960 pf output capacitance c oss 330 reverse transfer capacitance c rss 300 total gate charge q g v ds = - 4 v, v gs = - 8 v, i d = - 4.4 a 20 30 nc total gate charge q g v ds = - 4 v, v gs = - 4.5 v, i d = - 4.4 a 12 18 gate-source charge q gs 1.5 gate-drain charge q gd 3.1 gate resistance r g f = 1 mhz 1 5.1 10.2 tu r n - o n d e l ay t i m e t d(on) v dd = - 4 v, r l = 1.1 i d ? - 3.5 a, v gen = - 4.5 v, r g = 1 20 30 ns rise time t r 20 30 turn-off delay time t d(off) 40 60 fall time t f 10 15 tu r n - o n d e l ay t i m e t d(on) v dd = - 4 v, r l = 1.1 i d ? - 3.5 a, v gen = - 8 v, r g = 1 10 15 rise time t r 10 15 turn-off delay time t d(off) 35 55 fall time t f 10 15 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c - 1.4 a pulse diode forward current i sm - 20 body diode voltage v sd i s = - 3.5 a, v gs = 0 v - 0.8 - 1.2 v body diode reverse recovery time t rr i f = - 3.5 a, di/dt = 100 a/s, t j = 25 c 35 55 ns body diode reverse recovery charge q rr 14 25 nc reverse recovery fall time t a 16 ns reverse recovery rise time t b 19
document number: 64847 s10-0720-rev. c, 29-mar-10 www.vishay.com 3 vishay siliconix si2305cds typical characteristics 25 c, unless otherwise noted output characteristics on-resistance vs. drain current and gate voltage gate charge 0 5 10 15 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v ds -- drain-to-so u rce v oltage ( v ) i d - drain c u rrent(a) v gs = 5 v thr u 2 v v gs = 1.5 v v gs = 1 v 0.00 0.03 0.06 0.09 0.12 0.15 0 5 10 15 20 r ds(on) - on-resistance ( ) i d -- drain c u rrent (a) v gs =2.5 v v gs = 1. 8 v v gs = 4.5 v 0 2 4 6 8 04 8 12 16 20 i d = 4.4 a - gate-to-so u rce v oltage ( v ) q g - total gate charge (nc) v gs v ds = 6.4 v v ds =2 v v ds =4 v transfer characteristics capacitance on-resistance vs. junction temperature 0 1 2 3 4 5 0.0 0.3 0.6 0.9 1.2 1.5 v gs - gate-to-so u rce v oltage ( v ) i d - drain c u rrent(a) t c = 125 c t c = - 55 c t c = 25 c c rss 0 300 600 900 1200 1500 1 8 00 0246 8 c iss v ds - drain-to-so u rce v oltage ( v ) c - capacitance (pf) c oss 0.7 0. 8 0.9 1.0 1.1 1.2 1.3 1.4 - 50 - 25 0 25 50 75 100 125 150 t j - j u nction temperat u re (c) ( n ormalized) - on-resistance r ds(on) i d = 4.4 a v gs =2.5 v v gs =4.5 v , 1. 8 v
www.vishay.com 4 document number: 64847 s10-0720-rev. c, 29-mar-10 vishay siliconix si2305cds typical characteristics 25 c, unless otherwise noted source-drain diode forward voltage threshold voltage 0.1 1 10 100 0.0 0.3 0.6 0.9 1.2 t j = 150 c v sd - so u rce-to-drain v oltage ( v ) i s - so u rce c u rrent (a) t j =25 c 0.1 0.2 0.3 0.4 0.5 0.6 0.7 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a v gs(th) ( v ) t j - temperat u re (c) on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient 0.00 0.02 0.04 0.06 0.0 8 0.10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 r ds(on) - on-resistance ( ) v gs - gate-to-so u rce v oltage ( v ) i d = 2 a, t j = 25 c i d = 4.4 a, t j = 25 c i d = 2 a, t j = 125 c i d = 4.4 a, t j = 125 c 0 5 10 15 20 25 30 po w er ( w ) time (s) 10 1000 0.1 0.01 0.001 100 1 safe operating area, junction-to-ambient v ds - drain-to-so u rce v oltage ( v ) * v gs > minim u m v gs at w hich r ds(on) is specified 100 1 0.1 1 10 0.01 10 i d - drain c u rrent (a) 0.1 t a = 25 c single p u lse limited b yr ds(on) * b v dss limited dc 1 s, 10 s 100 ms 10 ms 1 ms
document number: 64847 s10-0720-rev. c, 29-mar-10 www.vishay.com 5 vishay siliconix si2305cds typical characteristics 25 c, unless otherwise noted * the power dissipation p d is based on t j(max) = 150 c, using junction-to-case thermal resi stance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determ ine the current rating, when this rating falls below the package limit. current derating* 0 2 4 6 8 0 25 50 75 100 125 150 t c - case temperat u re (c) d - drain c u rrent (a) i power, junction-to-case 0.0 0.4 0. 8 1.2 1.6 2.0 25 50 75 100 125 150 t c - case temperat u re (c) po w er dissipation ( w )
www.vishay.com 6 document number: 64847 s10-0720-rev. c, 29-mar-10 vishay siliconix si2305cds typical characteristics 25 c, unless otherwise noted vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?64847 . normalized thermal transient im pedance, junction-to-ambient 10 -3 10 -2 0 0 0 1 0 1 1 10 -1 10 -4 100 0.2 0.1 0.05 0.02 sq u are w a v ep u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1 0.1 0.01 d u ty cycle = 0.5 t 1 t 2 n otes: p dm 1. d u ty cycle, d = 2. per unit base = r thja =175 c/ w 3. t jm -- t a =p dm z thja (t) t 1 t 2 4. s u rface mo u nted single p u lse normalized thermal transient impedance, junction-to-foot 1 0.1 0.01 d u ty cycle = 0.5 sq u are w a v ep u lse d u ration (s) n ormalized effecti v e transient thermal impedance 10 -3 10 -2 1 10 -1 10 -4 0.02 single p u lse 0.1 0.2 0.05
vishay siliconix package information document number: 71196 09-jul-01 www.vishay.com 1 sot-23 (to-236): 3-lead b e e 1 1 3 2 s e e 1 d a 2 a a 1 c s e a ting pl a ne 0.10 mm 0.004" c c l 1 l q g au ge pl a ne s e a ting pl a ne 0.25 mm dim millimeters inches min max min max a 0.89 1.12 0.0 3 5 0.044 a 1 0.01 0.10 0.0004 0.004 a 2 0.88 1.02 0.0 3 46 0.040 b 0. 3 5 0.50 0.014 0.020 c 0.085 0.18 0.00 3 0.007 d 2.80 3 .04 0.110 0.120 e 2.10 2.64 0.08 3 0.104 e 1 1.20 1.40 0.047 0.055 e 0.95 bsc 0.0 3 74 ref e 1 1.90 bsc 0.0748 ref l 0.40 0.60 0.016 0.024 l 1 0.64 ref 0.025 ref s 0.50 ref 0.020 ref q 3 8 3 8 ecn: s-0 3 946-rev. k, 09-jul-01 dwg: 5479
an807 vishay siliconix document number: 70739 26-nov-03 www.vishay.com 1 mounting little foot sot-23 power mosfets wharton mcdaniel surface-mounted little foot power mosfets use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. see application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfet s, ( http://www.vishay.com/doc?72286 ), for the basis of the pad design for a littl e foot sot-23 power mosfet footprint . in converting this footprint to the pad set for a power device, designers must make tw o connections: an electrical connection and a thermal connection, to draw heat away from the package. the electrical connections for the sot-23 are very simple. pin 1 is the gate, pin 2 is the source, and pin 3 is the drain. as in the other little foot packages, the drai n pin serves the additional function of providing the thermal connection from the package to the pc board. the total cross section of a copper trace connected to the drain may be adequate to carry the current required for the application, but it may be inadequate thermally. also, heat spreads in a circular fashion from the heat source. in this case the drain pin is the heat source when looking at heat spread on the pc board. figure 1 shows the footprint with copper spreading for the sot-23 package. this pattern shows the starting point for utilizing the board area available for the heat spreading copper. to create this pattern, a plane of copper over lies the drain pin and provides planar copper to draw heat from the drain lead and start the process of spreading the heat so it can be dissipated into the ambient air. this pattern uses all the available area underneath the body for this purpose. figure 1. footprint with copper spreading 0.114 2.9 0.059 1.5 0.0394 1.0 0.037 0.95 0.150 3.8 0.081 2.05 since surface-mounted packages are small, and reflow soldering is the most common way in whic h these are affixed to the pc board, ?thermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum power trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low-impedance path for heat to move away from the device.
application note 826 vishay siliconix document number: 72609 www.vishay.com revision: 21-jan-08 25 application note recommended minimum pads for sot-23 0.106 (2.692) recommended mi nimum pads dimensions in inches/(mm) 0.022 (0.559) 0.049 (1.245) 0.029 (0.724) 0.037 (0.950) 0.053 (1.341) 0.097 (2.459) return to index return to index
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.
|
